At Lightelligence, we’re building computational machines that are solving problems in ways that have never been done before. We’re looking for a physical design engineer.
What you’ll do at Lightelligence:
Define back-end physical design methodology for ASIC tapeouts
Feasibility analysis, wiring studies
Define ASIC clocking methodology & rules for ASIC blocks and full-chip and define and own clocking architecture, reset and power sequencing strategy for ASICs
Floorplanning, synthesis, place & route, timing and design closure
Custom placement of critical blocks (digital and analog)
BS or MS in a relevant discipline such as Electrical Engineering and at least 5-7 years experience
Experience with ASIC physical design flow from feasibility to signoff using commercial EDA tools
Track record of successful tapeouts of ASICs of significant scope (size, frequency, power)
Willingness to learn new skills and do the work necessary to succeed.