Packaging Engineer - Integrated Silicon Photonics

Summary of Role

  • We are seeking a packaging engineer to collaborate with our electronics and photonics teams on the development of our high-bandwidth, low-latency nanophotonic processor. 

 

Responsibilities

  • Define the packaging solution for both the photonic die and electronic die
  • Engage with vendors to explore technology cooperation opportunities

 

Requirements

  • 5+ years of industrial packaging experience with wide knowledge of assembly processing; for example, wafer grinding, dicing, die attach, stacking, flip chip, wirebond, encapsulation, etc.
  • Experience of manufacturing, and assembly process related to silicon photonics; for example, optical grating or edge coupler for SMF, on package TEC, NTC thermistor, etc.
  • Knowledge of quality testing
  • Self-motivated and proactive; comfortable with limited supervision
  • Excellent communication skills

 

Preferred Skills

  • Experience with Copper Pillar Bump, Flip Chip and TSV assembly
  • Experience in chip on wafer (CoW) and chip on chip (CoC) wafer processing and assembly processes
  • Experience with photonic die and electronic die integration
  • Experience of thermal and mechanical optimization for system packaging
  • Experience product from NPI to HVM release through an OSAT partner